As semiconductor technology advances into the nanometer realm, such as 45 nm and below, various fabrication challenges arise. For example, breakdown voltage (VBD) and time dependent dielectric breakdown (TDDB) can be affected by relatively smaller dielectric spacing, relatively smaller interconnect pitch sizing, and other design factors resulting from sizing constraints of integrated circuits. VBD corresponds to a maximum voltage difference that can be applied to a dielectric material before the dielectric material collapses and conducts, which can lead to permanent physical or molecular changes to the dielectric material, such as a weakened path through the dielectric material. TDDB corresponds to a breakdown of MOSFETs that results from a formation of a conducting path through gate oxide to a substrate due to electron tunneling when the MOSFET is operating close to or beyond a specified operating voltage. In another example, current leakage can occur at an interface between two layers, such as between a dielectric layer and another layer. Such current leakage can increase as the length of the interface decreases. For example, an interface between a dielectric layer and an etch stop layer can be relatively small because the interface is bound between two structures, such as metal lines or vias, formed within the dielectric layer.